Modern computer systems are comprised of a plurality of processors, each performing dedicated functions. By using multiple processors, improved throughput is obtained.
A block diagram which illustrates the modularity of a modern computer system is set forth in FIG. 1. Computer system 100 illustrates a computer system architecture which may apply, for example, to an A16 mainframe (manufactured by Unisys Corporation, Blue Bell, Pa.). As illustrated by FIG. 1, the plurality of processors may be segregated into two separate partitions, with first domain 120 occupying one partition and second domain 130 occupying another partition. In this way, each partition is able to independently execute isolated tasks.
In some computer systems, multiple segregated processors (i.e. multiple domains) may be included in each partition for higher levels of independent but concurrent processing. Alternatively, if required, the two partitions can be combined to intercommunicate for processor intensive task execution. As a further alternative, first domain 120 may exist with second domain 130 deleted.
For simplicity, the components within computer system 100 will be described with regard to first domain 120. However, it is understood that many of the components found in first domain 120 are also found in second domain 130 (if second domain 130 is included).
A central processing module (CPM) 122 is responsible for many types of code execution. As one example, CPM 122 executes the operating system--referred to as the Master Control Program (MCP). Each program executed by CPM 122 performs separate procedures, referred to as "tasks".
Terminal 160 receives user instructions (for example, through a keyboard) and transfers the user instructions to the MCP being executed by CPM 122. Results of various tasks being executed by CPM 122 are communicated to the user by terminal 160.
Input/output module (IOM) 124 coordinates input/output (I/O) operations. IOM 124 is comprised of a plurality of units which coordinate I/O operations. One type of unit included in IOM 124 is input/output unit (IOU) 141. IOU 141 performs high level I/O functions such as the scheduling of I/O jobs, the selection of data paths over which I/O jobs are performed, the gathering of job statics and the management of I/O devices. Another type of unit included in IOM 124 is task control unit (TCU) 142. TCU 142 provides allocating and de-allocating of events, maintaining the status of tasks running on the system, performing of task priority computations and scheduling the execution of tasks.
For simplicity, CPM 122 and IOM 124 (and any other central processing modules and I/O modules in computer system 100) will each be referred to as requestors.
Memory storage module (MSM) 128 includes various memory components where program code and data may be stored. CPM 122 is able to communicate with MSM 128. Thus, for example, CPM 122 executes program code (e.g. the code for the MCP) stored in MSM 128. In addition, IOM 124 is able to communicate with MSM 128. Each requestor includes a memory cache to facilitate data storage and retrieval operations with MSM 128.
State access module (SAM) 126 provides host maintenance logic. SAM 126 is capable of viewing the state of CPM 122, IOM 124, and MSM 128.
Console (or coprocessor) 150 is coupled to each module (CPM 122, IOM 124, SAM 126 and MSM 128). Console 150 displays the state of each module and the state of MSM 128. Console 150 also invokes software routines--maintenance access commands (MACs)--which are executed by SAM 126 for providing data transfer functions to or between console 150 and requestors.
In accordance with the prior art, CPM 122 and IOM 124 include modularized hardware architectures which are capable of performing data processing. However, as is well known in the art, such hardware architectures perform processing responsive to microcode loaded therein. The loaded microcode directs the hardware to perform the transfer of data between various internal components (e.g. processors, requestors, memory, registers, etc.) according to predetermined timing sequences.
The ability to alter microcode within CPM 122 or IOM 124 facilitates modification of the operation of CPM 122 and IOM 124. Put another way, should a modification in the operation of CPM 122 and IOM 124 be desired, expensive hardware modifications are typically not necessary. All that is required is to load different microcode into these devices.
In accordance with the prior art, it is common for computer systems to stop processing and come to a complete halt in order to load new microcode. After restarting the system, tasks that were interrupted at the time of system halt typically cannot simply "resume" execution at the point of interruption. Instead, tasks may be started from their respective beginnings with their previous results (or intermediate results) lost. Thus, downtime of the computer system is required with a significant impact on system productivity. Furthermore, interrupted tasks may require complete re-execution.
For example, many computer systems may have hundreds of tasks currently in various stages of execution. The complete stoppage of such a computer system is a significant inconvenience and major expense to the users of such systems. Furthermore, after the new microcode has been loaded, either a system re-boot or special types of re-configuration action are required. This may be significantly time consuming and require the use of expensive engineering resources.
Various system reconfigurations may be attempted to load new microcode without incurring the aforementioned difficulties. Such reconfigurations are tedious to implement and often not successful.